arXiv:2609.21157v1 Announce Type: new Abstract: Large Language Model (LLM) agents are increasingly being explored for chip design, but most existing approaches operate directly at RTL. We ask whether agents can design better chips by leveraging higher-level abstractions. We compare Direct RTL Design, Agent-based HLS Design, Post-Compiler HLS Refinement, and Post-HLS RTL Refinement, and combine Age

So what

What this event means by reading role—not a longer recap.

BuilderBuilders of agentic EDA or hardware-generation tools can adopt the AHRR two-stage HLS-then-RTL-refinement workflow instead of prompting agents directly at RTL.
ResearcherThe paper provides an 11-task FPGA benchmark and code artifacts comparing four agent design flows, giving a baseline for higher-abstraction agentic chip design

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Score dimensions

Higher total means read first. Each bar is one factor we use to rank the system pool. How we score

RelevanceHow tightly this is about AI.: 82
ImpactHow much this could change the field or the market.: 55
NoveltyHow new this is versus a recap.: 70
CredibilityHow much we trust the source.: 97
ActionabilityWhether a reader can do something with it.: 45